I've just spend a little time to understand your schematic. I've understood most part of it, but some obscure points still remains. Could you help me to figure it out and check if I didn't misunderstand the schematic ?
So first of all, the simplest part (my two cents) is the output stage composed of a current source (J7/R67) and some current mirrors (Q2/Q20) which will duplicate the current reference (call it ib) to the diamond buffers via Q22/Q24 and Q1/Q19.
This diamond buffers (Q13/Q14 and Q15/Q16) will drive the output transistor (Q3/Q18 and Q4/Q17).
My question is how do you calculate the current biasing (class A) of these output transistor ? This current depends on R28, R17 and R21 (and respectively R19, R20, R22) isn't it ? Something like ib*R28/R21 (considering the Vbe of Q14 and Q3 are the same...) ?
Which value did you chose for Re (the emitter degeneration resistance depend of the biaising current of the diamond buffer i presume) ?
Why did you include 1ohm resistance R32 and R25 ? It increases the output impedance which was null (or very very small).
Last thing, i probably didn't search well but i don't find the datasheet of the J2SK117.
Now, the most tricky part : the input stage !
I'm not
The IPS is composed of a floating complementary JFET-LTP (J1,J2,J3,J4,R3,R33). I'm not comfortable with the JFET because i never use it, so i don't exactly understand how it works. However, i suppose the N and P channel have to match to provide good performances. I mean the two halves have to match together. If not the gain of each half will be different and it will introduce harmonic distortion ? So to build this amp, we have to care about the JFETs matching ? Why not using only an N-channel JFET input ?
A last, the VAS. The signals arrive at the emitter of Q7, Q11, Q9 ans Q5 (with or without phase shit).
The voltage between D1/D2 and D3/J5 is fixed by the leds (J5/R54 imposes a constant current throwing the leds so the forward voltage is constant).
Edit : ahh ! just figure out the Q7/Q8 are juste a cascode stage ! I didn't recognize it ! Normaly, on traditional cascode, the signal arrives on the base of Q7.
Except these findings, i don't really understand how it works : what is R61 ? Same for R55/C3 : is it a feedback cap for stability ?
Last question : you say that for the moment the gain is 8. How to calculate it ? It depends on R16 and R16 (R52 and R24) ?
I know that it is a lot of questions, i'm sorry for that. But your amp is very interesting !
If you don't mind, could you share the LTSpice schematics with the components (JFETs and output BJT are not include with LTSpice) so i could simulate it to improve my understanding of the amp !
Thanks a lot for sharing your experience here !
Adhafera